1. Field of the Invention
The invention relates to a radiation hardened master latch having redundant clock input circuits, suitable for use in a radiation hardened programmable phase frequency divider designed for implementation in deep submicron CMOS technology. The invention also relates to a design structure embodied in a machine readable medium for designing, manufacturing and/or testing such a radiation hardened master latch.
2. Background Information
CMOS circuits used in space applications are subject to single event upsets (SEU's) as a result of exposure to radiation consisting of alpha particles or neutrons. The charge induced by a single SEU hit can be as high as 1 picoCoulomb (pC), and can have a 2 milliAmpere (mA) amplitude with a 1 nanosecond (ns) period. When a programmable phase frequency divider (PPFD) used in such a space application is running at a frequency lower than 200 Megahertz (MHz), an SEU hit with 1 pC charge may not always cause a soft error if the timing of the SEU does not fall within the window for the set and hold times of any of the flip flops in the PPFD. In such case, a dual interlocked cell (DICE) type flip flop design, such as the one described in Weizhong Wang and Haiyan Gong, “Sense Amplifier Based RADHARD Flip Flop Design,” IEEE Transactions on Nuclear Science, Vol. 51, No. 6 (December 2004), may be used. However, a PPFD fabricated in deep submicron technology can run at frequencies in the Gigahertz (GHZ) range. In this case, the vulnerable timing window for set and hold of the PPFD's D-type flip flops (DFF's) will always be covered by the typical 1 ns period of an SEU hit.
A radiation hardening technique to ensure that the PPFD continues to function properly in a radiation environment is disclosed in U.S. patent application Ser. No. 11/419,008, by William Mo, filed on May 16, 2006 and assigned to IBM Corporation (“Mo '008”). The Mo '008 application, which is incorporated herein by reference, is directed to a PPFD for space applications that is implemented in CMOS technology, consisting in the exemplary embodiment of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division according to an integer division number, between 1 and 8, that is input to the combinational logic circuits. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. The PPFD outputs a pulse train representing the clock source frequency divided in accordance with the division number.
As disclosed in further detail in the Mo '008 application, each of the radiation hardened D-type flip flops in the exemplary embodiment includes a master latch having a clock input, first and second data and complementary data inputs, and first and second data and complementary data outputs, which is connected in tandem to a slave latch having first and second data and complementary data inputs, and first and second data and complementary data outputs. Operation of the D-type flip flop is immune to a single event upset affecting at most one of the four data inputs to the master latch or to the slave latch.
The Mo '008 application further discloses that the radiation hardened master latch 20 of the exemplary embodiment, shown in FIG. 1 hereof, includes: a first master latch half circuit 10 having a clock input CLK, first and second data and complementary data inputs DIN_0, DIN_1, DINB_0 and DINB_1, feedback and complementary feedback inputs Q_DUAL and QB_DUAL, and data and complementary data outputs Q and QB; and a second master latch half circuit 10 identical to the first master latch half circuit and having a corresponding clock input, first and second data and complementary data inputs, feedback and complementary feedback inputs and data and complementary data outputs. In the master latch, the respective clock inputs of the first and second master latch half circuits are connected together in parallel; the respective first and second data and complementary data inputs of the first and second master latch half circuits are connected together in parallel; the data and complementary data outputs of the first master latch half circuit are cross connected to the feedback and complementary feedback inputs of the second master latch half circuit; and the data and complementary data outputs of the second master latch half circuit are cross connected to the feedback and complementary feedback inputs of the first master latch half circuit. In the absence of SEU's, the first and second pairs of data inputs to the master latch have nominally the same input voltage levels. Operation of the master latch is immune to a single event upset affecting at most one of the four data inputs to the master latch.
FIG. 2 hereof is a schematic diagram of each one of the two identical master latch half circuits 10 of the exemplary embodiment disclosed in the Mo '008 application. While each exemplary master latch half circuit effectively utilizes pairs of data and complementary data inputs and outputs to mitigate the effect of SEU's, it can be seen from FIG. 2 that there is no similar protection for the clock node CLK. At the clock node CLK in FIG. 2, there is a single inverter 12, the output of which is connected to the gates of transistors T10, T11 and T12. The inverter 12 would typically be implemented using the semiconductor circuit shown schematically in FIG. 3. If the n+ drain diffusion 31 of the NFET device 32 of the inverter 12 were to be hit, even with a low energy radiation particle, it would cause the master latch to lose state during the evaluate phase, when the inverter 12 output, CKB_TOP is being held to a logical 1, and the master latch would function incorrectly. Under these circumstances, what is required is an improved clock input circuit that is designed to ensure that the exemplary master latch of the Mo '008 application continues to function properly in a radiation environment.